1. Field of the Invention
This invention relates to a semiconductor integrated circuit using a wafer level package.
2. Description of the Related Art
In recent years, the wafer level package (hereafter referred to as a WLP) is in widespread use. The WLP is a general name for a package that has a size equivalent to a die size housed in it, and is directed to realizing high density packaging. It is also called a chip size package.
In general, the WLP is manufactured at a semiconductor fab, and is shipped to a module fab after a pre-shipment test. Various kinds of electronic components including the WLP are mounted onto a circuit board to manufacture various kinds of modules at the module fab. The modules manufactured there are shipped to end customers after their circuit functions are tested.
Technologies mentioned above are disclosed in Japanese Patent Application Publication No. 2000-188305, for example.
The WLP is more vulnerable to mechanical damage in handling or in mounting it onto the circuit board compared with a resin mold package. Potential defects resulting from the damage are chipping or cracking of the die, separation of a resin covering a surface of the die and the like, which are prone to be caused in a periphery of the die.
However, the WLP having the defect such as the chipping or cracking of the die or the separation of the resin may pass the circuit function test at the module fab in some cases, depending on a location or a degree of the defect. Therefore, the module in which the WLP having the defect is mounted may be shipped to the end customer, and a failure in quality may be caused there.
This invention is directed to controlling so that the WLP having the defect as described above is prevented from being shipped.